I. Field of the Invention:
This invention relates to a method for manufacturing a semiconductor device and, in particular, a method for manufacturing a semiconductor device, which includes an improved step of forming source and drain regions.
II. Description of the Prior Art:
In the manufacture of a MOS type semiconductor device, the microminiaturization technique has quickly been implemented, as known, whereby elements are microminiaturized with a high performance and integration density. In actual practice, a MOS type semiconductor device having a channel length of, for example, 1 .mu.m or less has been developed. In the microminiaturized MOS type semiconductor device, a very high electric field is involved between the source and drain regions, in particular, between the source and drain regions in an n-channel MOS transistor, presenting various problems due to holes and electrons produced under a high electric field. As one example, a threshold voltage varies (rises) due to the electrons injected into a gate oxide film or a substrate current is abnormally increased due to the holes injected into the semiconductor substrate. This problem also arises in a complementary MOS semiconductor device (hereinafter referred to as a CMOS).
A method for manufacturing a MOS type semiconductor device, for example, an n-channel MOS IC has been proposed in which a high electric field between the source and drain regions is alleviated. The manufacturing method will be explained below by referring to FIGS. 1A to 1E.
First, a field oxide film 2 is formed, as an element isolating region, on the surface of a p type silicon substrate 1 of a crystal orientation (100) and an oxide film is formed on the substrate 1 at an island-like element area isolated by the field oxide film 2. Then, a phosphorus-doped polycrystalline silicon film is deposited on the whole surface of the resultant structure. The polycrystalline silicon film is patterned to form a gate electrode 3 on the oxide film overlying the respective element area. The oxide film is selectively etched with the gate electrode 3 as a mask to form a gate oxide film 4. With the gate electrode 3 and field oxide film 2 as masks, an n type impurity, such as phosphorus, is ion implanted at an acceleration voltage of 20 KeV and a dose of 1.times.10.sup.13 cm.sup.-2 into the resultant structure to form a layer of a lower concentration level of phosphorus. After the resultant structure has been heat-treated, an n type diffusion layer (5a, 5b) is formed at the element area of the substrate 1 as shown in FIG. 1A.
Then, a CVD-SiO.sub.2 film 6 of, for example, 4,000 .ANG. is deposited on the whole surface of the substrate, as shown in FIG. 1B. The CVD-SiO.sub.2 film 6 is etched by an RIE (Reactive Ion Etching) method down to an extent corresponding to about the thickness of the CVD-SiO.sub.2 film 6, leaving an SiO.sub.2 wall 7 on the side surface of the gate electrode 3 and the gate oxide film 4, as shown in FIG. 1C. With the gate electrode 3, wall 7 and field oxide film 2 as masks, an n type impurity, such as arsenic, is ion implanted at an acceleration voltage of 40 KeV and a dose of 3.times.10.sup.15 cm.sup.-2. The resultant structure is heat-treated in an nitrogen atmosphere at 900.degree. C. to permit the activation of arsenic. In this way, an n.sup.+ type diffusion layer (8a, 8b) of a high concentration level is formed. As a result, as shown in FIG. 1D, a source region 9 comprised of an n.sup.- type diffusion layer 5a and n.sup.+ type diffusion layer 8a is formed and a drain region 10 comprised of the n.sup.- type diffusion layer 5b and n.sup.+ type diffusion layer 8a is formed at the surface of the resultant structure.
Then, an SiO.sub.2 film 11 is deposited on the surface of the resultant structure and contact holes (12) are formed. An Al film is evaporated on the SiO.sub.2 film 11, followed by a patterning step. As a result, an Al interconnection layer 13 is connected through the contact hole 12 to the n type source region 9 and an Al interconnection layer 14 is connected through the contact hole 12 to the drain region 10. In this way, an n-channel MOS IC is formed as shown in FIG. 1E.
According to the above-mentioned conventional method, a source region 9 is comprised of the n.sup.- type diffusion layer 5a of a low concentration level located in proximity to the gate electrode 3 and the n.sup.+ type diffusion layer 8a of a high concentration level located remote from the gate electrode 3 and is formed at the element of the p type silicon substrate; and a drain region 10 is comprised of the n.sup.- type diffusion layer of a low concentration level located in proximity to the gate electrode 3 and the n.sup.+ type diffusion layer 8b of a high concentration level located remote from the gate electrode 3 and is formed at the element area of the p type silicon substrate. In this way, the so-called LDD structure is implemented, whereby it is possible to suppress the generation of a high electric field between the above-mentioned source and drain regions.
However, the above-mentioned conventional method poses the following problems:
(1) In the step as shown in FIG. 1D, the CVD-SiO.sub.2 film 6 is etched, by the RIE method, down to an extent corresponding to the thickness thereto, leaving the wall 7 on the side surfaces of the gate electrode 3. In this step, however, the thinning of the field oxide film 2 occurs due to the overetching of the field oxide film 2. As shown in FIG. 2, the field oxide film 2 for isolating one MOS transistor from another is narrowed so that a distance L between the n.sup.+ layers 8 and 8 before the step of the RIE may be reduced to a distance Le to cause a lowered breakdown voltage.
(2) Since the wall 7 is formed by the RIE method, damage by ions is liable to occur at those surface portions of the silicon substrate where the source and drain regions are formed, prominently lowering the element characteristic.
(3) When the oxide film is selectively etched with the gate electrode 3 as the mask to form the gate oxide film 4, "undercutting" occurs on the gate oxide film, lowering the breakdown voltage between the gate electrode and the source and drain regions and thus deteriorating reliability.
A CMOS manufacturing method similar to the method shown in FIGS. 1A to 1E has also been proposed. This method will be explained below by referring to FIGS. 3A to 3G.
First, a p type semiconductor layer (p-well) 22 is selectively formed in an n type silicon substrate 1 of a crystal orientation (100). A field oxide film 23 is formed, as an element isolation region, at the substrate 21 and p-well 22, leaving island-like regions there. An oxide film is formed on the island-like regions of the substrate 21 and p-well 22 which are isolated by the field oxide film 23. Then, a phosphorus-doped polycrystalline silicon film is deposited on the surface of the resultant structure. The polycrystalline silicon film is patterned to form a gate electrode (24, 25) on the oxide film overlying the element region and, with the gate electrode (24, 25) as a mask, the oxide film is selectively etched, leaving the gate oxide film (26, 27) as shown in FIG. 3A.
Then, a resist pattern 28 is formed by a photolithography on that surface of the n type element region, and with the resist pattern 28, gate electrode 24 and field oxide film 23 as masks an n type impurity, such as phosphorus, is ion implanted into the p-well 22 at an acceleration voltage of 20 KeV and a dose of 1.times.10.sup.13 cm.sup.-2 to form a phosphorus ion injected layer (29a, 29b) of a low concentration level, as shown in FIG. 3B. After the removal of the resist pattern 28, a resist pattern 30 is so formed by the photolithography as to cover the p-well 22. With the resist pattern 30, gate electrode 25 and field oxide film 23 as masks, a p type impurity, such as boron, is ion implanted into the n type substrate 21 at an acceleration voltage of 40 KeV and a dose of 1.times.10.sup.15 cm.sup.-2 to form a boron ion injected layer (31a, 31b) as shown in FIG. 3C.
After the removal of the resist pattern 30, a CVD-SiO.sub.2 film 32 of, for example, 4,000 .ANG. is deposited on the surface of the resultant structure, followed by a heat treatment for 30 minutes in a nitrogen atmosphere at, for example, 900.degree. C. As shown in FIG. 3D, the phosphorus ion injected layer (29a, 29b) is activated to form an n.sup.- type diffusion layer (33a, 33b) of a low concentration level, while, on the other hand, the boron ion injected layer (31a, 31b) is activated to form p.sup.+ type source and drain regions (34, 35). The CVD-SiO.sub.2 film 32 is etched, by the RIE method, down to an extent corresponding to about the thickness thereof, leaving a wall 36 on the side surfaces of the gate electrode 24 and gate oxide film 26 and on the side surfaces of the gate electrode 25 and gate oxide film 27 as shown in FIG. 3E.
Then, a resist pattern, not shown, is so formed by the photolithography as to cover the element area in the n type substrate 21. With the resist pattern, gate electrode 24, wall 36 and field oxide film 23 as masks, an n type impurity, such as arsenic, is ion implanted into the element area in the p-well at an acceleration voltage of 40 KeV and a dose of 3.times.10.sup.15 cm.sup.-2. After the removal of the resist pattern, heat treatment is performed in an nitrogen atmosphere at, for example, 900.degree. C. As a result, the arsenic ion injected layer is activated to form n.sup.+ type diffusion layers (37a, 37b). As a result, a source region 38 is formed, comprising the n.sup.- type diffusion layer 33a and n.sup.+ type diffusion layer 37a. A drawn region 39 is also formed which comprises the n.sup.- type diffusion layer 33b and n.sup.+ type diffusion layer 37b. An SiO.sub.2 film 40 is deposited on the whole surface of the resultant structure and an opening is formed as a contact hole (41, 41b, 41c, 41d). An Al film is evaporated on the SiO.sub.2 film 40, followed by a patterning step. An Al interconnection layer 42 is connected through a contact hole 41a to the n type source region 38, an Al interconnection layer 43 is connected respectively through contact holes 41c and 41b to the drain regions 35 and 39, and an Al interconnection layer 44 is connected through the contact hole 41d to the p.sup.+ type source region 34. In this way, a CMOS device is manufactured as shown in FIG. 3G.
According to the conventional method, an n-channel transistor so formed is of the so-called LDD type in which the source region comprises the n.sup.- type diffusion layer 33a of a low conductivity level located in proximity to the gate electrode 24 and the n.sup.+ type diffusion layer 37a of a high concentration level located remote from the gate electrode 24 and the drain region 39 comprises the n.sup.- type diffusion layer 33b of a low concentration level located in proximity to the gate electrode 24 and the n.sup.+ type diffusion layer 37 of a high concentration level located remote from the gate electrode 24. It is therefore possible to suppress the generation of a high electric field between the above-mentioned source and drain regions.
The method as explained in connection with FIGS. 3A to 3G presents the same problems as those as set out in connection with FIGS. 1A to 1E. Furthermore, the following problems arise therefrom. According to the method, in order to avoid a possible "offsetting" of the source and drain regions 34 and 35 of the p-channel transistor, the source and drain regions 34 and 35 are formed before the walls 36 are formed on the side surfaces of the gate electrode (24, 25). Even after the p.sup.+ type source and drain regions 34 and 35 are formed, the resultant structure is subjected to a heat treatment at a high temperature for the formation of the n.sup.+ type diffusion layers 37a and 37b, causing a redistribution of an impurity to occur at the source and drain regions with a deeper junction. As a result, the p-channel transistor reveals a marked "short channel effect", leading to a variation etc. of the threshold voltage. In order to prevent a possible redistribution of the impurity from occurring at the p.sup.+ type source and drain regions 34 and 35, one method is to form p.sup.+ type source and drain regions through the ion implantation of a p type impurity after the CVD-SiO.sub.2 wall 36 has been removed. In this method, however, the field oxide film 23 is etched during the removal of the CVD-SiO.sub.2, causing the thinning of the film as has been explained in connection with the problem (1) above.